The rising costs of creating a mask set, combined with customers wishing to manufacture low-volume designs, has led the semiconductor industry to introduce the multi-project wafer. The multi-project wafer allows multiple companies' IP or individual companies with multiple IP to reside on the same reticle (unit cell), enabling these companies to share the costs of production while maintaining acceptable yields. With mask costs constantly increasing, it has also become increasingly popular to prototype designs using multi-project wafer runs.
Adding a multi-project wafer methodology to a fabrication facility that is only set up to handle single-project wafers is a complex process. For example, floor plan design and wafer dicing, once simple, becomes a process requiring much thought and planning, to make sure that the die (also referred to as discrete chip or chips) are properly aligned and that no chips are destroyed when making multiple dicing passes of different-size chips. In addition, many of the software and hardware tools used in the process remain set up to handle only single-project wafers, and must be “customized” into dealing with multi-project wafers. The picking tool, for instance, can only pick one chip type on each picking pass.
At the same time, complexity within the multi-project wafer has been rapidly increasing. Typical multi-project wafers can have anywhere from 2 to 30+ unique chips (i.e., IP and sometime size) within a single reticle. This has made it difficult to process multi-project wafers, not only for obvious technical reasons, but also because care must be taken to protect each customer's IP (that is, each customer is only allowed to see yield/process data for their chips).
Another contributing factor to the difficulty in processing multi-project wafers is that the costs to the service provider have increased with increasing number of customers. For example, the wafer manufacturer must gather all the customers' design data, make sure this data comes in at the same time, and interface with customers after the manufacturing process is complete to determine the customers' requirements on final chip selection and packaging. Also, chip selection has become difficult for both customers and engineers because of the need to give each customer manufacturing and process data and help them correlate that data with specific chips to be picked. For example, each set of customer picks must be translated into many industry-standard wafer maps that will be forward to the picking tools. Lastly, each customer has specific requests for processing which cause a drain on engineer time as the engineer must manually edit wafer maps and tool settings to comply with these demands.
The current system has also caused an exponential increase in engineering time and idling time on the tool, as processing a multi-project wafer currently takes as much or more time than processing the equivalent number of single-project wafers. In addition, when customers want to see data for their chips, they must request it from an engineer, who has to prepare the data, filter out other customers' information, and then translate the data into a useful form that the customer can understand. This process does not fit within the on-demand model that the industry would like to adopt.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.